-------------------------------------------------------------------------------
-- regfile_rtl.vhd
-------------------------------------------------------------------------------
--
-- This file is part of SKUMLI.
-- Copyright (C) 2011 Davide Giuseppe Monaco (black.ralkass@gmail.com)
--
-- SKUMLI is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- SKUMLI is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with SKUMLI.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
architecture rtl of regfile is

  type vectorial_vector is array (31 downto 0) -- should be 2^M
    of std_logic_vector(N - 1 downto 0);

  signal register_file : vectorial_vector;

begin -- rtl

  dout0 <= register_file(conv_integer(s));
  dout1 <= register_file(conv_integer(t));

  main: process (rst, clk, we)
  begin -- main

    if rst = '1' then
      for i in 0 to 31 loop
        register_file(i) <= (others => '0');
      end loop;

    else
      if clk'event and clk = '1' and we ='1' then
        register_file(conv_integer(d)) <= din;
      end if;

    end if;

  end process main;
end rtl;
